數字設計：原理與實(shí)踐（英文版 第5版）簡(jiǎn)介，目錄書(shū)摘

內容簡(jiǎn)介:　　本書(shū)是數字設計領(lǐng)域的經(jīng)典教材，是作者牢固的理論功底、嚴謹的學(xué)術(shù)風(fēng)范與豐富的實(shí)踐經(jīng)驗的完美融合。原理方面涵蓋高級（HDL）、低級（電子電路）以及“廣泛中間級”（門(mén)電路、觸發(fā)器和一些較高級的數字設計構件）的多層次基礎知識，更加方便不同專(zhuān)業(yè)的教學(xué)內容選??；實(shí)踐方面專(zhuān)注于Verilog一種實(shí)現語(yǔ)言，強調基于FPGA的設計，并且添加了更多應用實(shí)例。

作者簡(jiǎn)介:　　約翰·F. 韋克利（John F. Wakerly） 于斯坦福大學(xué)獲得電子工程博士學(xué)位。他目前是思科系統公司廣域網(wǎng)業(yè)務(wù)部主管工程項目的副總裁，還是斯坦福大學(xué)的兼職教授。他在數字設計、微型計算機體系結構、計算機可靠性等方面出版了50多部著(zhù)作，并在電信與網(wǎng)絡(luò )領(lǐng)域擁有13項專(zhuān)利。

目錄:Contents
1 INTRODUCTION 1
1.1 About Digital Design1
1.2Analog versus Digital3
1.3Analog Signals7
1.4Digital Logic Signals7
1.5Logic Circuits and Gates9
1.6Software Aspects of Digital Design13
1.7Integrated Circuits16
1.8Logic Families and CMOS19
1.9CMOS Logic Circuits20
1.10Programmable Devices25
1.11Application-Specific ICs27
1.12Printed-Circuit Boards28
1.13Digital-Design Levels29
1.14The Name of the Game33
1.15Going Forward34
Drill Problems34
2 NUMBER SYSTEMS AND CODES 35
2.1Positional Number Systems36
2.2Binary, Octal, and Hexadecimal Numbers37
2.3Binary-Decimal Conversions39
2.4Addition and Subtraction of Binary Numbers42
2.5Representation of Negative Numbers44
2.5.1Signed-Magnitude Representation
2.5.2Complement Number Systems
2.5.3Two’s-Complement Representation
2.5.4Ones’-Complement Representation
2.5.5Excess Representations
2.6Two’s-Complement Addition and Subtraction48
2.6.1Addition Rules
2.6.2A Graphical View
2.6.3Overflow
2.6.4Subtraction Rules
2.6.5Two’s-Complement and Unsigned Binary Numbers
2.7Ones’-Complement Addition and Subtraction52
2.8Binary Multiplication54
2.9Binary Division56
2.10Binary Codes for Decimal Numbers57
2.11Gray Code602.12Character Codes62
2.13Codes for Actions, Conditions, and States64
2.14n-Cubes and Distance66
2.15Codes for Detecting and Correcting Errors67
2.15.1Error-Detecting Codes
2.15.2Error-Correcting and Multiple-Error-Detecting Codes
2.15.3Hamming Codes
2.15.4CRC Codes
2.15.5Two-Dimensional Codes
2.15.6Checksum Codes
2.15.7m-out-of-n Codes
2.16Codes for Transmitting and Storing Serial Data78
2.16.1Parallel and Serial Data
2.16.2Serial Line CodesReferences82
Drill Problems83
Exercises85
3SWITCHING ALGEBRA AND COMBINATIONAL LOGIC89
3.1Switching Algebra91
3.1.1Axioms
3.1.2Single-Variable Theorems
3.1.3Two- and Three-Variable Theorems
3.1.4n-Variable Theorems
3.1.5Duality
3.1.6Standard Representations of Logic Functions
3.2Combinational-Circuit Analysis104
3.3Combinational-Circuit Synthesis110
3.3.1Circuit Descriptions and Designs
3.3.2Circuit Manipulations
3.3.3Combinational-Circuit Minimization
3.3.4Karnaugh Maps
3.4Timing Hazards122
3.4.1Static Hazards
3.4.2Finding Static Hazards Using Maps
3.4.3Dynamic Hazards
3.4.4Designing Hazard-Free CircuitsReferences126
Drill Problems128Exercises129
4DIGITAL DESIGN PRACTICES133
4.1Documentation Standards133
4.1.1Block Diagrams
4.1.2Gate Symbols
4.1.3Signal Names and Active Levels
4.1.4Active Levels for Pins
4.1.5Constant Logic Signals
4.1.6Bubble-to-Bubble Logic Design
4.1.7Signal Naming in HDL Models
4.1.8Drawing Layout
4.1.9Buses
4.1.10Additional Schematic Information
4.2Circuit Timing154
4.2.1Timing Diagrams
4.2.2Propagation Delay
4.2.3Timing Specifications
4.2.4Sample Timing Specifications
4.2.5Timing Analysis Tools
4.3HDL-Based Digital Design165
4.3.1HDL History
4.3.2Why HDLs?
4.3.3EDA Tool Suites for HDLs
4.3.4HDL-Based Design FlowReferences172
Drill Problems
174Exercises176
5VERILOG HARDWARE DESCRIPTION LANGUAGE177
5.1Verilog Models and Modules179
5.2Logic System, Nets, Variables, and Constants184
5.3Vectors and Operators189
5.4Arrays193
5.5Logical Operators and Expressions194
5.6Compiler Directives197
5.7Structural Models198
5.8Dataflow Models203
5.9Behavioral Models (Procedural Code)205
5.9.1Always Statements and Blocks
5.9.2Procedural Statements
5.9.3Inferred Latches
5.9.4Assignment Statements
5.9.5begin-end Blocks
5.9.6if and if-else Statements
5.9.7case Statements
5.9.8Looping Statements
5.10Functions and Tasks220
5.11The Time Dimension224
5.12Simulation225
5.13Test Benches226
5.14Verilog Features for Sequential Logic Design232
5.15Synthesis232
References233
Drill Problems234
Exercises235
6BASIC COMBINATIONAL LOGICELEMENTS237
6.1Read-Only Memories (ROMs)240
6.1.1ROMs and Truth Tables
6.1.2Using ROMs for Arbitrary Combinational Logic Functions
6.1.3FPGA Lookup Tables (LUTs)
6.2Combinational PLDs246
6.2.1Programmable Logic Arrays
6.2.2Programmable Array Logic Devices
6.3Decoding and Selecti