超大規模集成電路布線(xiàn)技術(shù)（新視野電子電氣科技叢書(shū)）簡(jiǎn)介，目錄書(shū)摘
2020-10-16 09:53
來(lái)源：京東
作者：京東
超大規模集成電路布線(xiàn)技術(shù)（新視野電子電氣科技叢書(shū)）
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內容簡(jiǎn)介:
本書(shū)作者Pinaki Mazumder教授是IEEE Fellow和AAAS Fellow，在EDA領(lǐng)域有30年以上的教學(xué)、科研和工程經(jīng)歷。
本書(shū)匯集電子設計自動(dòng)化領(lǐng)域包括作者在內的研究者的*新成果，聚焦超大規模集成電路布線(xiàn)技術(shù)，從串行與并行布線(xiàn)模型開(kāi)始，到各種基本布線(xiàn)算法，兼顧芯片設計中的特定情況，重點(diǎn)討論了大量的工業(yè)界實(shí)用的特殊類(lèi)型布線(xiàn)與*新并行布線(xiàn)器。
本書(shū)注重基礎，主要研究迷宮布線(xiàn)算法、總體布線(xiàn)算法、詳細布線(xiàn)算法（即通道布線(xiàn)與開(kāi)關(guān)盒布線(xiàn)算法等）和特殊布線(xiàn)算法，具有較高的通用性和實(shí)用性，有望推動(dòng)超大規模集成電路布線(xiàn)工具的持續發(fā)展。
本書(shū)既涉及EDA領(lǐng)域“大家”的重要成果，也涵蓋作者及其團隊30多年的杰出研究，適合計算機與半導體行業(yè)從業(yè)的工程師、電子設計自動(dòng)化方面的教學(xué)者閱讀，也適合研究VLSI電路布局布線(xiàn)算法的高年級碩士生、博士生以及研究學(xué)者參考。
作者簡(jiǎn)介:
目錄:1 INTRODUCTION
1.1 Sequential routing models
1.2 Parallel routing models
1.3 Organization
2 MAZE ROUTING ALGORITHMS
2.1 Maze routing
2.2 Variants of maze routing
2.3 Parallel maze routing
2.4 Case Study: A custom VLSI design for concurrent maze routing
2.5 Line-probe routing
3 GLOBAL ROUTING ALGORITHMS
3.1 Global routing
3.2 Global routing graphs and region ordering
3.3 Sequential global routers
3.4 Concurrent approaches to global routing
3.5 Parallel global routing algorithms
3.6 Global routing for analog designs
3.7 Case Study: A complete global routing system for SOG designs
4 CHANNEL ROUTING ALGORITHMS
4.1 Introduction
4.2 Left edge Algorithm (LEA) and its variants
4.3 Doglegged channel touters
4.4 Multi-Layer Channel Routers
4.5 Gridless approaches
4.6 Specialized channel routers
4.7 Parallel channel routing
4.8 Case Study (MARS): A detailed gridless general area router
5 SWITCHBOX ROUTING ALGORITHMS
5.1 Switchbox routing
5.2 Parallel switchbox routing algorithms
5.3 Case Study: A parallel multi-layer detailed routing framework
6 SPECIALIZED AND TECHNOLOGY-SPECIFIC ROUTING ALGORITHMS
6.1 Power and ground routing
6.2 Timing driven routing
6.3 Single-row routing for PCBs
6.4 Routing algorithms for FPGAs
6.5 Routing for MCM designs
6.6 Case Study: High Performance Interconnect Design and Analysis
7 CONCLUSION
7.1 Commercial Tools
7.2 Academic Layout Systems
REFERENCES
1.1 Sequential routing models
1.2 Parallel routing models
1.3 Organization
2 MAZE ROUTING ALGORITHMS
2.1 Maze routing
2.2 Variants of maze routing
2.3 Parallel maze routing
2.4 Case Study: A custom VLSI design for concurrent maze routing
2.5 Line-probe routing
3 GLOBAL ROUTING ALGORITHMS
3.1 Global routing
3.2 Global routing graphs and region ordering
3.3 Sequential global routers
3.4 Concurrent approaches to global routing
3.5 Parallel global routing algorithms
3.6 Global routing for analog designs
3.7 Case Study: A complete global routing system for SOG designs
4 CHANNEL ROUTING ALGORITHMS
4.1 Introduction
4.2 Left edge Algorithm (LEA) and its variants
4.3 Doglegged channel touters
4.4 Multi-Layer Channel Routers
4.5 Gridless approaches
4.6 Specialized channel routers
4.7 Parallel channel routing
4.8 Case Study (MARS): A detailed gridless general area router
5 SWITCHBOX ROUTING ALGORITHMS
5.1 Switchbox routing
5.2 Parallel switchbox routing algorithms
5.3 Case Study: A parallel multi-layer detailed routing framework
6 SPECIALIZED AND TECHNOLOGY-SPECIFIC ROUTING ALGORITHMS
6.1 Power and ground routing
6.2 Timing driven routing
6.3 Single-row routing for PCBs
6.4 Routing algorithms for FPGAs
6.5 Routing for MCM designs
6.6 Case Study: High Performance Interconnect Design and Analysis
7 CONCLUSION
7.1 Commercial Tools
7.2 Academic Layout Systems
REFERENCES
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